1. Field
Example embodiments relate to a flash memory device, and methods of manufacturing and operating the same. Other example embodiments relate to a flash memory device that may offset undesirable reliability due to degradation of a portion into which electrons or holes are injected, and methods of manufacturing and operating the flash memory device.
2. Description of the Related Art
Non-volatile memory devices are semiconductor memory devices that may preserve stored data even when there is no supply of power. Representative non-volatile memory devices may be flash memory devices. Each of a plurality of memory cells constituting flash memory may include a cell transistor having a gate structure in which a floating gate storing charges, e.g., data, and a control gate controlling the floating gate may be sequentially stacked. Program or erase operations may be performed in the cell transistor using the Fowler-Nordheim (F-N) tunnelling mechanism.
In order to satisfy the demand for expanding the memory capacity of the flash memory device, the size of the memory cells has been reduced. Also, according to the reduction in the size of the memory cells, a height of the floating gate in a vertical direction may be reduced. However, the size of the floating gate may limit the reduction in the size of the flash memory device. In order to deal with this limitation, a charge trap flash (CTF) memory device including a charge trap layer instead of a floating gate has been developed. The CTF memory device may utilize a shifting threshold voltage as charges are trapped in the charge trap layer. The CTF memory device may be smaller than a flash memory device that stores charges in a floating gate.
FIGS. 1A and 1B are cross-sectional views illustrating the program and erase operations of a conventional CTF memory device. Referring to FIGS. 1A and 1B, a memory cell constituting the conventional CTF memory device may include a tunnel oxide layer 1 formed on a channel region 8 of a semiconductor substrate and allowing charges to tunnel therethrough, a charge trap layer 3 formed on the tunnel oxide layer 1 and allowing the charges tunneling through the tunnel oxide layer 1 to be trapped therein, a blocking oxide layer 5 formed on the charge trap layer 3 and preventing or reducing the charges passing through the charge trap layer 3 from moving upward, and a control gate 7 formed on the blocking oxide layer 5. The channel region 8 may be formed in the semiconductor substrate. In a memory cell array, a device isolating region 9 may be formed by shallow trench isolation (STI) to define the channel region 8 and electrically separate the memory cells. The tunnel oxide layer 1, the charge trap layer 3, the blocking oxide layer 5, and the control gate 7 may be formed on the channel region 8 and the device isolating region 9. The memory cell may be defined by the channel region 8.
Referring to FIG. 1A, in a program mode, a higher voltage (for example, 16V to 17V) may be applied to the control gate 7 and a lower voltage (for example, 0V) may be applied to the channel region 8. Thus, electrons may be injected from the channel region 8 into the charge trap layer 3 and then trapped in the charge trap layer 3. A lower voltage, e.g., a voltage Vbody of 0V, may be applied to the semiconductor substrate and the channel region 8.
Referring to FIG. 1B, in an erase mode, a low voltage (for example, 0V) may be applied to the control gate 7, the channel region 8 may be floated, and a high voltage (for example, a voltage Vbody of 17 to 18V) may be applied to the semiconductor substrate. Thus, the electrons stored in the charge trap layer 3 may be released from the charge trap layer 3 to the channel region 8, or removed due to recombination with holes injected into the charge trap layer 3 from the channel region 8.
As illustrated in FIG. 2, a threshold voltage may be determined at a central portion A′ of the channel region 8 adjacent to the channel region 8 and the tunnel oxide layer 1. However, in the program or erase mode, electrons or holes may be injected into the central portion A′, thereby degrading the tunnel oxide layer 1. As illustrated in FIG. 3, degradation of the tunnel oxide layer 1 may result from traps generated in a portion of the tunnel oxide layer 1 into which the electrons or holes are injected. Such traps may affect the channel region 8 located below and shift a programmed threshold voltage. Accordingly, when the portion into which electrons or holes are injected is degraded in the program or erase mode, the threshold voltage may be shifted, thereby degrading the reliability of the CTF memory device.